1. Field of the Invention
The present invention relates to phase comparing circuits and PLL circuits, and particularly to a phase comparing circuit which is used for a PLL circuit operating stably at high speed, and also particularly to a PLL circuit which can easily be miniaturized.
2. Description of the Background Art
The PLL (Phase Locked Loop) circuits which have been widely used in the field of communication to establish synchronization with received data are now increasingly provided inside the LSIs to establish synchronization with input clocks with speeding up of the LSIs. The PLL circuits are used, for instance, for ATM (Asynchronous Transfer Mode) switches used in the ATM communication. For example, FIG. 49 is a conceptional diagram for illustrating the structure of an ATM switch which is described in "LSIs for ATM Switches", Mitsubishi Denki Giho, Vol. 67, No. 3, pp. 42-45, 1993 etc. In FIG. 49, 80 denotes an A-LSI having functions of phasing of input/output cells, header extraction of input cells, parity generation of input cells, parity check of output cells, various kinds of error detection etc. and holding two lines of both input and output in one chip, 81 denotes a B-LSI having buffering and switching functions for cells, eight being used for bit slices and one being used for parity, 82 denotes a C-LSI having functions of generating addresses for reading/writing of buffer memories and control signals of spatial switches, and 83 denotes a PLL circuit (Phase-Locked Circuit) provided in each B-LSI 81 for establishing synchronization between input clock of each B-LSI 81 and an internal clock. The demand for higher speed operations of the ATM switches is increasing year by year, and the demand is on the increase for such high speed operations as can be adapted to frequencies of several hundred MHz.
FIG. 50 is a block diagram showing the structure of a general PLL circuit. A PLL circuit 105 includes a phase comparator (also referred to as PC hereinafter) 101, a charge pump (also referred to as CP hereinafter) 102, a loop filter (also referred to as LF hereinafter) 103 and a voltage-controlled oscillator (also referred to as VCO hereinafter) 104. Generally, the "PC" is referred to as including CP, but the CP is shown as one block separated from the PC herein for convenience of description.
The function of each block will be described below. In the PC, the input clock CLKref and the internal clock CLKint are compared in phase with each other, and if the internal clock CLKint is lagging behind the input clock CLKref, "1" is outputted as an output UP and if it is ahead of the same, "1" is outputted as an output DOWN. When the output UP is "1", the CP 102 turns on to charge a capacitor of the LF 103.
When the output DOWN is "1", the CP 102 turns on to discharge the capacitor of the LF 103. The result of the phase comparison is thus integrated in the LF 103 to be a control voltage for the VCO 104, based on which the oscillation frequency of the VCO 104 changes. The output clock of the VCO 104 is distributed to an internal circuit having a load 107 through a clock driver (also referred to as a DRV hereinafter) 106. The internal clock CLKint is fed back as an input of the PLL circuit.
FIG. 51 is a circuit diagram showing one example of the structure of a conventional phase comparator. The phase comparator circuit shown in FIG. 50 is configured using four flip-flops (also referred to as FF). The four FFs are each comprised of two NAND gates NA 50 and NA 51 as depicted as the FF 110.
The input clock CLKref is provided via an inverter IN 50 as set input of the FF 110. The internal clock CLKint is provided via an inverter IN 51 as set input of the FF 113. The output e of the FF 110 is inputted to a 4-input NAND gate NA 60, and the output f of the FF 113 is inputted to the NAND gate NA 60. The outputs g and h of the FFs 111 and 112 are also inputted to the NAND gate NA 60.
The output of the NAND gate NA 60 is applied to the reset inputs of the FF 111 and FF 112, and the output of the NAND gate NA 60 is applied to the inputs of AND gates AN 50 and AN 51. The outputs g and h of the FF 111 and FF 112 are applied to another input of each AND gate AN 50 and AN 51 respectively. The output of the AND gates AN 50 and 51 are applied to the reset inputs of the FF 110 and FF 113 respectively. Then inversion outputs of the FF 110 and FF 113 are outputted as an output UP and an output DOWN, respectively.
The operation of this circuit will be described below referring to the timing chart of FIG. 52. It is assumed that before the time t100, as the initial state, the input clock CLKref and the internal clock CLKint are "0" and the output UP and the output DOWN are "1", that is, the nodes e and f are at "0" and the nodes g, h and i are at "1".
At the time t100, if the input clock CLKref attains "1" earlier, the FF 110 is set and the node e goes to "1" and the output UP goes to "0". After that, at the time t101, when the internal clock CLKint attains "1", the FF 113 is set, and the node f goes to "1" and the output DOWN becomes "0", and the node i goes to "0" simultaneously. This resets all the FFs, the outputs UP and DOWN go back to "1", and the nodes g and h go to "0", and thus the node i goes back to "1".
Next, at the time t102, when the input clock CLKref goes back to "0", the node e goes back to "0", the FF 111 is set and the node g goes back to "1". In the same way, at the time t103, when the internal clock CLKint goes back to "0", the node f goes to "0", the node h goes to "1", and thus it returns to the initial state.
As described above, the output UP is outputted only for a period corresponding to the phase difference between the input clock CLKref and the internal clock CLKint, while only a spike-like pulse appears for a moment in the output DOWN. On the other hand, when the internal clock CLKint attains "1" first, the output DOWN is outputted for a period corresponding to the phase difference in contrast to the case described above, and a spike-like pulse momentarily appears in the output UP. Now, if the NAND gate NA 51 in the FF 110 (FF 113) is made 3-input and the AND gates AN 50 and AN 51 are omitted, the spike-like pulses will not appear. Since this circuit compares the phase on leading edges (rising edges) of the clock, it operates even when the duty of the clock changes. As output of FF is fed back to input, however, it takes time until states of all FFs become stable. Accordingly, the conventional PLL circuit has had a problem that it can not be satisfactorily adapted to a clock with a frequency higher than several hundred MHz, and for example, it has had a disadvantage that it can not be applied to a high-speed clock over 500 MHz.
FIG. 53 is a state transition diagram showing the operation of the phase comparator shown in FIG. 51. In this state transition diagram, when (.uparw., X) is indicated, for example, ".uparw." represents a rise of a signal and "X" represents an arbitrary state. A state of the input clock CLKref is indicated on the left side and a state of the internal clock CLKint is indicated on the right side in the parentheses. Furthermore, .alpha. represents a state in which the output UP and the output DOWN are both "1" in the phase comparator, .beta. represents a state in which the output UP only is "0" in the phase comparator, .gamma. represents a state in which the output DOWN only is "0" in the phase comparator, and .delta. represents a state in which the output UP and the output DOWN are both "0" in the phase comparator. Also, "*" shows that the state .delta. instantly makes transition to the state .alpha. without being stabilized at the state .delta.. As can be seen from this state transition diagram, it must go by way of the state .delta. to transfer from the state .beta. and the state .gamma. to the state .alpha., with the result that the phase comparison operation becomes slow.
Next, FIG. 54 is a circuit diagram for describing the structure of the conventional PLL circuit. FIG. 54 shows a part of the PLL circuit, where the structure from the phase comparator (PC) 101 to the loop filter (LF) 103 shown in FIG. 50 is illustrated. Shown as an example of the charge pump (CP)102 is a charge pump 121 including a P-channel transistor Q70 for supplying current from VDD to LF and an N-channel transistor 071 for extracting current from LF to GND, and shown as an example of the LF 103 is a lag-type filter 122 including a resistor Re2 and a capacitor C2.
The time constant of the LF given from product of the resistance value of the resistor Re2 and the capacity of the capacitor C2 is deeply related to the locking lime, stability, jitter etc. of the PLL, where a large time constant is required in consideration of the stability and jitter. However, there has been a problem that large areas are needed to provide capacitors with large capacity inside chips.
As described above, according to the conventional phase comparing circuit, when the CLKint attains "1" first, DOWN is outputted only for a period corresponding to the phase difference conversely to the description above and a spike-like pulse momentarily appears in UP. Now, if the NAND gate NA 51 of the FFs 110 and 113, for example, are made 3-input and the AND gates AN 50 and AN 51 are omitted, the spike-like pulse will not appear. However, since the phase is compared at a leading edge of clock in this circuit, it operates even if the duty of the clock changes. However, in the conventional phase comparator, it takes time until the states of all FFs become stable because outputs of the FFs are fed back to inputs. Accordingly, the conventional PLL circuit has had a problem that it can not be satisfactorily adapted to clocks with frequencies higher than several hundred MHz, and for example, it can not be applied to high speed clocks over 500 MHz.
Also, in the conventional PLL circuit, the time constant of LF is deeply related to locking time, stability, jitter etc. of PLL and a large time constant is required in consideration of the stability and the jitter, therefore it has had a problem that large areas are necessary to build capacitors with large capacity in chips.